1. Field of the Invention
The present invention relates to a diamond film field effect transistor having a channel layer made of semiconducting diamond, and a method of manufacturing the transistor.
2. Description of the Related Art
Diamond is a well known electrical insulating material. It is excellent in heat-resistance. It can exhibit p-type semiconducting property when doped with boron (B). Vapor phase synthesis has been recently established as a method of forming diamond films. Using semiconducting diamond films attempts have been made to manufacture electronic devices, such as diodes and transistors, which are excellent in heat-resistance.
FIG. 8 is a sectional view of a prior art metal-insulator-semiconductor field effect transistor (hereinafter, referred to as "MISFET") using monocrystalline diamond films (Unexamined Japanese Patent Publication No. HEI 1-158774). In this transistor, a B-doped monocrystalline p-type semiconducting diamond film 12 (hereinafter, referred to as "p-layer") is formed by vapor-phase synthesis on a monocrystalline diamond substrate 11. An undoped (or high resistance) diamond film 13 (hereinafter, referred to as "i-layer") is then laminated on the p-layer 12. The i-layer 13 is subjected to patterning in a specified shape. After that, a source electrode 14 and a drain electrode 16 are formed on the p-layer 12, and a gate electrode 15 is formed on the i-layer 13. The film thickness of the p-layer 12 is about 0.5 .mu.m.
In a prior art manufacturing method shown in FIGS. 9A to 9E, a source electrode and a drain electrode selectively grow in self-alignment to a gate electrode (Unexamined Japanese Patent Publication No. HEI 5-29609). A p-layer 22 is coated on a substrate 21 (FIG. 9A); a mask 27 is formed on the p-layer 22 in a shape on which a source electrode and a drain electrode are to be formed (FIG. 9B); and an i-layer 23 is formed on the p-layer 22 exposed from the mask 27 so as to slightly extend on the mask 27 (FIG. 9C). The mask 27 is then removed (FIG. 9D), and a source electrode 24, a drain electrode 25 and a gate electrode 26, which are all made of the same material, are deposited (FIG. 9E).
In another prior art manufacturing method shown in FIGS. 10A to 10E (Unexamined Japanese Patent Publication No. HEI 5-29608), a p-layer 32 is deposited on a substrate 31. A metal film 34 and a lift-off film 36 are (FIG. 10A) formed on the p-layer 32. The metal film 34 and the lift-off film 36 are then etched (FIG. 10B), and an i-layer 33 as a gate insulating layer is formed on the p-layer 32 (FIG. 10C). A gate electrode 35 is coated (FIG. 10D) over the whole surface, and the lift-off film 36 is removed (FIG. 10E), thus forming an MISFET structure.
The above-described prior art techniques, however, have the following disadvantages. First, in the prior art technique shown in FIGS. 9A to 9E, the i-layer 23 is required to grow in the shape shown in FIG. 9D. However, the umbrella-like projection of diamond shown in FIG. 9D is difficult to be formed because the density of generating nuclei of diamond on the mask 27 is small in practice. The reference disclosing this prior art technique also shows a modification which are illustrated in FIG. 11. In this modification, masks 43 and 44 are stepwise formed on a p-layer 43 provided on a substrate 41 for forming an umbrella-like projection of an i-layer 45. However, even in this method, the it 45 is difficult to grow i-layer 45 stepwise on the masks 43 and 44. As a result, it is difficult to actually form the shape structure shown in FIG.. 11. To manufacture MISFITS with a high repeatability, the length of the umbrella-like projection must be accurately controlled. However, such a control cannot be obtained by this method. It is difficult to fabricate a fine device which has source to drain electrode distance of a few microns using the selective growth process disclosed in this prior art.
The contact resistance between the p-layer 22 and the electrodes (24 and 25) is the critical disadvantage of this prior art technique. To lower the contact resistance, the device must be thermally treated; however, it cannot be lowered to be less than about 10.sup.-4 .OMEGA.cm.sup.2 only by heat-treatment. To lower the contact resistance to a practical value of 10.sup.-5 .OMEGA.cm.sup.2 or less, it is essential to form a diamond layer of low resistivity doped with B at a high concentration (hereinafter, referred to as "p.sup.+ layer") between the source and drain electrodes 24, 25 and the p-layer 22 by ion implantation or in situ doping. However, this is impossible using the prior art technique.
In this prior art technique, the gate electrode 26 is made of a metal, such as Ti, so it is easy to form carbides. Accordingly, the characteristics of the gate electrode are deteriorated by thermal treatment at high temperatures (for example, 600.degree. C. or more).
On the other hand, in the prior art shown in FIGS. 10A to 10E, the films 34 and 36 must be etched by plasma until the p-layer 32 is exposed from the surface in the process shown in FIG. 10B. At this time, the surface of the p-layer 32 is damaged by the plasma-etching, which causes a problem in deteriorating the characteristics of the p-layer 32. The high contact resistance is the problem which can not be circumvented in this prior art.